The invention relates to an integrated circuit comprising a cascode current mirror, a bias stage for biassing the cascode current mirror, a first supply voltage terminal for receiving a first supply voltage, and a second supply voltage terminal for receiving a second supply voltage, the cascode current mirror having an input terminal for receiving an input current, an output terminal for supplying an output current, a first cascoded MOS transistor having a gate coupled to the input terminal, a source coupled to the supply voltage terminal, and a drain, a first cascode MOS transistor having a gate coupled to the bias stage, a source coupled to the drain of the first cascoded MOS transistor, and a drain coupled to the input terminal, a second cascoded MOS transistor having a gate coupled to the gate of the first cascoded MOS transistor, a source coupled to the source of the MOS transistor 21, and a drain, and a second cascode MOS transistor having a gate coupled to the gate of the first cascode MOS transistor, a source coupled to the drain of the second cascoded MOS transistor, and a drain coupled to the output terminal.
Such an integrated circuit, which converts an input current into an output current by means of a cascode current mirror, can be utilized in a diversity of chips.
Such an integrated circuit is known inter alia from U.S. Pat. No. 4,618,815. In the known integrated circuit the bias stage comprises a current source and a MOS transistor coupled as a diode. Since the current source and the MOS transistor are serially coupled between the two supply voltage terminals a current generated by the current source produces a voltage across the MOS transistor, which voltage is applied between the gates of the two cascode MOS transistors and the second supply voltage terminal. As a result of the voltage the two cascode MOS transistors and, indirectly, the two cascoded MOS transistors are biassed, which two cascoded MOS transistors should be operated in a saturation mode in order to ensure an undistorted current transfer of the cascode current mirror. Since the cascoded MOS transistors have a drain-source voltage which varies depending upon a current through the two cascoded MOS transistors, the voltage between the gates of the two cascode MOS transistors and the second supply voltage terminal should have value which guarantees saturation of the cascoded MOS transistors. As a result, the value of the voltage between the gates of the two cascode MOS transistors and the second supply voltage terminal should exhibit a margin to cope with a variation of the drain-source voltage.
A disadvantage of such an integrated circuit is that the output voltage between the first supply voltage terminal and the output terminal is comparatively small owing to the margin.